Direct Digital Frequency Synthesizer with CORDIC Algorithm and Taylor Series Approximation for Digital Receivers

In this document we are presenting a new approach to design an optimised Direct Digital Frequency Synthesizer (DDFS) for complex demodulation used in digital receivers. For that, we suggest an adaptation of the phase to sine converter by combining the two following techniques: 1) an optimized COordinate Rotation DIgital Computer (CORDIC) algorithm 2) the principle of Taylor series approximation. To validate our proposed approach, a DDFS with 8 Hz tuning frequency resolution and 20 bits output data (for sine and cosine waves) is being implemented in Xilinx FPGA device giving a maximum operating frequency of more than 306 MHz and a Spurious Free Dynamic Range (SFDR) of 112 dBc. To prove the good performances of the proposed approach, we compared it favorably with several existing DDFS architectures.